Examples of semiconductor devices include various devices, including field effect transistors (FETs), light emitting diodes (LEDs), and the like. For those semiconductor devices, for example, Group III-V semiconductors made of compounds of Group III and Group V elements are used.
A Group III nitride semiconductor using Al, Ga, In, or the like as a Group III element and using N as a Group V element has a high melting point and a high dissociation pressure of nitrogen, which makes it difficult to perform bulk single crystal growth. Further, conductive single crystal substrates having large diameter are not available at low cost. Accordingly, such a semiconductor is typically formed on a sapphire substrate.
However, a sapphire substrate is electrically insulating; accordingly, electric current does not flow in the substrate. Therefore, in recent years, methods of fabricating a vertical structure LED chip or the like, in which III nitride semiconductor layers are supported by a support have been studied, in which method the III nitride semiconductor layers including a light emitting layer is formed on a growth substrate such as a sapphire substrate, and after the support is separately bonded onto the III nitride semiconductor layers, the sapphire substrate is separated (lifted off).
As an example of those methods, a method of manufacturing vertically structured III nitride semiconductor LED chips that is described in WO 2011/055462 (PTL 1) will be explained with reference to FIGS. 19A to 20B. FIGS. 19A to 19F are schematic cross-sectional views illustrating the steps of a method of manufacturing conventional vertically structured III nitride semiconductor LED chips 500. First, a semiconductor laminate 503 is formed on a growth substrate 501 with a lift-off layer 502 therebetween by sequentially stacking a first conductivity type III nitride semiconductor layer 504, a light emitting layer 505, and a second conductivity type III nitride semiconductor layer 506 (FIG. 19A). Next, the semiconductor laminate 503 and the lift-off layer 502 are partly removed to expose the growth substrate 501, thereby forming a plurality of separate semiconductor structures 507 are formed by partly removing the semiconductor laminate 503 (FIG. 19B). Subsequently, a support 512 is formed, which integrally supports the plurality of semiconductor structures 507 and also serves as a lower electrode (FIG. 19C). Further, the lift-off layer 502 is removed using a chemical lift-off process, thereby separating the growth substrate 501 from the plurality of semiconductor structures 507 (FIG. 19D). After that, upper electrodes 516 are formed on the separation side of the semiconductor structures 507 (FIG. 19E); finally, the support 512 is divided by cutting or the like along the broken lines shown in FIG. 20A between the semiconductor structures 507, thus singulating the wafer into a plurality of LED chips 500 having respective semiconductor structures 507 supported by respective divided supports 512A (FIG. 19F).
FIG. 20A is a schematic top view of a wafer in a state of FIG. 19E where the plurality of semiconductor structures which have not been singulated are formed. FIG. 19E is a cross-sectional view taken along a broken line in FIG. 20A. FIG. 20B is a schematic side view of one of the LED chips 500 singulated along the broken lines in FIG. 20A. Thus, in PTL 1, through-grooves 514 are provided along cut lines of the singulation (broken lines) in portions of the support 512 located between adjacent semiconductor structures 507. Accordingly, when the lift-off layer 502 is removed as in FIGS. 19C to 19D, an etchant is supplied via the through-grooves 514 to surround the semiconductor structures 507. Further, the lift-off layer 502 right under the semiconductor structures 507 is etched from the outer peripheral portion of the semiconductor structures to the center portion thereof.
Here, in PTL 1, as shown in FIG. 20A, the transverse cross section of the semiconductor structures 507 has a circular shape or a 4 n-gon shape (“n” is a positive integer) having rounded corners. If the transverse cross section of the semiconductor structures has a 4 n-gon shape without rounded corners, X-shaped cracks extending from the vicinity of the corners to the center portion would be formed in the individual semiconductor structures at a considerable rate after the lift-off as shown in FIG. 21A. In PTL 1, the shape of the semiconductor structures is as described above, so that stresses can be prevented from being concentrated at the corners (the vectors of the etching proceeding from the periphery of the semiconductor structures meet) during etching; thus, the formation of the above X-shaped cracks can be prevented.